Many different types of substrates are used for various purposes in the electronics industry. For example, integrated circuits are conventionally fabricated on semiconductor-type substrates to form semiconductor devices such as, for example, memory devices, imaging devices, and electronic signal processor devices (i.e., often referred to as microprocessors). Such semiconductor-type substrates include, for example, full or partial wafers of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and other III-V- or II-VI-type semiconductor materials. Wafers include, for example, not only conventional wafers formed completely of a semiconductor material, but other substrates such as silicon-on-insulator (SOI)-type substrates, silicon-on-sapphire (SOS)-type substrates, and epitaxial layers of silicon supported by a layer of base material. Other types of substrates are used to form various other components and devices used in the electronics industry including, for example, circuit boards, contact cards, test carriers, package substrates, and interposer substrates. Such other types of substrates may comprise polymer materials, ceramic materials, metal materials, and composite materials, as well as a semiconductor material, usually silicon.
Substrates used in the electronics industry often carry conductive structures for communicating electrical signals and/or for providing electrical power to active elements of an electronic device. Such conductive structures include, for example, conductive traces (which conventionally extend in a generally horizontal direction relative to a major plane of the substrates), conductive vias (which conventionally extend in a generally vertical direction through at least a portion of the substrates), and conductive contact terminals (e.g., conductive pads) used for electrically interconnecting other conductive structures or devices to the conductive structures carried by the substrates.
It is often desirable to provide electrical communication through a substrate using the aforementioned conductive vias to electrically connect conductive traces and/or pads on one side of a substrate to conductive traces and/or pads on the opposing side of the substrate. As an example, two or more semiconductor devices (e.g., semiconductor dies or packages) may be stacked one on top of another to form a so-called “multi-chip module,” which may be used to reduce the mounting area required on a circuit board for each of the semiconductor devices thereof. In such multi-chip modules, it is necessary to establish electrical communication between each of the semiconductor devices within the stack and the circuit board. Therefore, conductive vias may be formed entirely through one or more of the semiconductor devices to allow at least one other semiconductor device stacked thereover to communicate electrically with the circuit board through the conductive vias. As another example, the conductive contact terminals on a semiconductor device may be physically arranged in a pattern that does not correspond to a pattern of conductive contact terminals on a higher-level substrate to which it is desired to electrically connect the semiconductor device. Therefore, it may be necessary to effectively redistribute the conductive contact terminals of either the semiconductor device or the higher-level substrate to enable electrical contact to be established therebetween. A so-called “redistribution layer” is often used to effectively redistribute the conductive contact terminals on a semiconductor device. A redistribution layer includes conductive traces that each extends over a surface of a substrate from a first location to a second location at which another conductive contact terminal may be provided. The second location may correspond to, and be complementary with, a location of a conductive contact terminal on another element or device. Additionally, conductive vias may provide electrical communication to conductive regions on the back side of a semiconductor device to facilitate back-side probing. Back-side probing may be useful in identifying any defects in the semiconductor device before it is further processed, packaged or assembled with other devices.
As used herein, the term “substrate” refers to any electronic structure or device that comprises a conductive via, or through which it is desired to form a conductive via. By way of example and not limitation, substrates may include semiconductor dies, full or partial semiconductor wafers, semiconductor devices (e.g., memory devices, imaging devices, and electronic signal processors), circuit boards, and layers of semiconductor, polymer, ceramic, or metal materials, or a combination thereof.
To form a conductive via, a via may be formed through a substrate using any one of a variety of methods, including mechanical drilling, laser ablation, and wet (chemical) or dry (reactive ion) etching. As used herein, the term “via” refers to a hole or aperture that extends through a substrate, while the phrase “conductive via” refers to a via that is at least partially filled with an electrically conductive material to form an electrical pathway extending through the via. Furthermore, a “through wafer interconnect” or “TWI” is a particular type of conductive via that extends substantially entirely through a full or partial semiconductor wafer, or through a semiconductor device formed from such a full or partial semiconductor wafer.
Optionally, the walls of the substrate within the via may be coated with a dielectric material. The dielectric material may comprise, for example, an oxide, a nitride, a polymer, or a glass. Methods of depositing and otherwise forming such layers of dielectric material are known in the art and may vary depending on the type of material used for the substrate and for the dielectric layer. The via may then be at least partially filled with a conductive material to form a conductive via. As an example, the conductive material may be deposited on one or more surfaces of the substrate within the via using methods such as electrolytic plating, electroless plating, vacuum evaporation (chemical vapor deposition and variants), and sputtering (also termed physical vapor deposition). Additionally, the via may be substantially entirely filled with the conductive material. For example, a conductive or conductor-filled epoxy may be deposited into the via in flowable form and subsequently cured, or a solder paste may be deposited into the via and subjected to a reflow process.
After a conductive via has been formed through a substrate, the substrate may optionally be thinned, a redistribution layer may optionally be formed on one or more major surfaces of the substrate, and/or conductive bumps (i.e., solder balls or other conductive elements in the form of columns, pillars, studs, etc.) may optionally be formed or placed on conductive terminals on the substrate.
Examples of known methods for foil ling conductive vias through substrates are found in, for example, U.S. Patent Application Publication No. 2007/0048994, published Mar. 1, 2007, now U.S. Pat. No. 7,517,798, issued Apr. 14, 2009, to Tuttle; U.S. Pat. No. 7,109,068, issued Sep. 19, 2006, to Akram et al.; and U.S. Patent Application Publication No. 2006/0289968, published Dec. 28, 2006, now U.S. Pat. No. 7,795,134, issued Sep. 14, 2010, to Sulfridge. The disclosure of each of the forgoing documents is incorporated herein in its entirety by reference.
There remains a need in the art for improved methods of forming conductive vias through substrates, and for forming conductive structures, such as redistribution layers, on such substrates.